搜索资源列表
SLAVE-FIFO-16BITS
- CY7C68013a的slavefifo的固件源代码，keil编写，以及使用FPGA向EP6端点写数据的verilog源代码，没有错误，可以编译成功!-CY7C68013a of slavefifo firmware source code, keil prepared using FPGA and write data to the endpoint EP6 verilog source code, no errors, you can compile successfully!
UART_RX
- 这是借鉴别人的带有FIFO的Verilog代码分享给大家，共同学习-This is learn from others with FIFO Verilog code for everyone to share, learn together
FIFO
- 利用verilog写的异步FIFO的一种写法-Using a written verilog write asynchronous FIFO
fifo
- 基于Verilog的fifo源码，经验证，有效，实用-very good
FIFO
- Nios ii fifo,用于MCU通过nios ii进行fifo通信,verilog格式.-Nios ii fifo, for MCU FIFO communication, through the Nios II Verilog format.
sync_FIFO
- asynchronous fifo verilog code
Synchronous-FIFO-
- 一个用verilog实现的同步fifo设计，压缩包里有word介绍设计中各信号的作用-Achieve a synchronous fifo with verilog design, compression bag has the role of word describes the design of the signals
fifo
- 深度256的异步fifo 使用verilog语言编写的，能够实现简单的读写，存储功能！-256 the depth of asynchronous FIFO
fifo
- FIFO源码以及测试文件基于ISE14，Verilog语言编写，全部工程。-FIFO based on source code and test files ISE14, Verilog language, the whole works.
Syn_FIFO
- 异步FIFO verilog fifo代码-Asynchronous FIFO verilog fifo Code
async_fifo
- 异步FIFO verilog 代码 复位到空，读侧以及写侧复位均可以使两侧同时复位，且基本同时放开。-ayschronized FIFO verilog code
fifo
- 本程序实现简单的fifo传输，并没有加其他的功能，试用芯片xilinx，verilog语言编写-The program implements a simple fifo transmission, and no other added features, try chip xilinx, verilog language
fifo
- 使用Verilog实现异步fifo的功能-Use Verilog implementation of asynchronous fifo functionality
fifo
- 关于FIFO的verilog源代码,可以很快的对FIFO做简单的了解-Verilog on the FIFO source code, you can quickly do a simple understanding of FIFO
FIFO
- 用verilog语言编写的FIFO文件，这是一种传统的按序执行方法，先进入的指令先完成并引退，跟着才执行第二条指令，希望能够帮助读者-With verilog language FIFO file, which is a traditional sequential execution method, first enter the command to finish and retire, followed by only the second instruction execution, h
fifo
- 异步FIFO的verilog实现，可以参考一下-Verilog asynchronous FIFO implementation, you can refer to
SOA_MAT
- VERILOG code for NOC FIFO -VERILOG code for NOC FIFO ..
fifofinal
- FIFO verilog学习时的基础编程练习。以8位输入，8位输出为例，输入输出采取不同时钟。 附加testbench。-first in first out
SDRAM-and-FIFO-for-DE1-SoC-master
- Verilog TUTORIAL for beginners. We had earlier published a Verilog tutorial that made use of the Xilinx ISE Simulator.
[verilog]dcfifo_256x32
- Dual-Clock FIFO, Depth: 256 Width: 32 USEDW: Y FULLL:Y EMPTY:Y-This is self-defined Dual-Clock FIFO, using logic lut resources.